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6613-1.4 04-01-98 t1/c2/d2 ep 1 characteristics subject to change without notice 1m X28ST010 128k x 8 bit high temperature, 5 volt, byte alterable e 2 prom features ? 185 c full functionality ? simple byte and page write single 5v supply self-timed ? no erase before write ? no complex programming algorithms ? no overerase problem ? highly reliable direct write? cell endurance: 10,000 write cycles data retention: 100 years higher temperature functionality is possible by operating in the byte mode. description the xicor X28ST010 is a 128k x 8 e 2 prom, fabricated with xicor's proprietary, high performance, ?oating gate cmos technology which provides xicor products superior high temperature performance characteristics. like all xicor programmable non-volatile memories the X28ST010 is a 5v only device. the X28ST010 features the jedec approved pinout for byte-wide memories, compatible with industry standard eproms. the X28ST010 supports a 256-byte page write operation, effectively providing a 19 m s/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. xicor e 2 proms are designed and tested for applications requiring extended endurance. data retention is speci?ed to be greater than 100 years. pin configurations v bb a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we nc a 14 a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 X28ST010 flat pack cerdip soic (r) X28ST010 (bottom view) 14 a 0 16 i/o 1 18 v ss 11 a 3 9 a 5 7 a 7 15 i/o 0 17 i/o 2 19 i/o 3 5 a 15 2 nc 36 v cc 20 i/o 4 21 i/o 5 34 nc 23 i/o 7 25 a 10 27 a 11 29 a 8 22 i/o 6 32 nc 24 ce 26 oe 28 a 9 30 a 13 13 a 1 12 a 2 10 a 4 8 a 6 4 a 16 3 v bb 1 nc 35 we 33 nc 31 a 14 6 a 12 pga preliminary
X28ST010 2 pin descriptions addresses (a 0 Ca 16 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, power consumption is reduced. output enable (oe ) the output enable input controls the data output buffers and is used to initiate read operations. data in/data out (i/o 0 Ci/o 7 ) data is written to or read from the X28ST010 through the i/o pins. write enable (we ) the write enable input controls the writing of data to the X28ST010. back bias voltage (v bb ) it is required to provide -3v on v bb pin. this negative voltage improves higher temperature functionality. pin names symbol description a 0 Ca 16 address inputs i/o 0 Ci/o 7 data input/output we write enable ce chip enable oe output enable v bb C3v v cc +5v v ss ground nc no connect functional diagram x buffers latches and decoder i/o buffers and latches y buffers latches and decoder control logic and timing 1m-bit e 2 prom array i/o 0 Ci/o 7 data inputs/outputs ce oe v cc v ss a 8 Ca 16 we a 0 Ca 7 v bb
X28ST010 3 device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control architecture eliminates bus contention in a system environment. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the X28ST010 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs ?rst. a byte write operation, once initiated, will automatically continue to completion, typically within 5ms. page write operation the page write feature of the X28ST010 allows the entire memory to be written in 5 seconds. page write allows two to two hundred ?fty-six bytes of data to be consecutively written to the X28ST010 prior to the commencement of the internal programming cycle. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 8 through a 16 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the initial byte write cycle, the host can write an additional one to two hundred ?fty-six bytes in the same manner as the ?rst byte was written. each successive byte load cycle, started by the we high to low transition, must begin within 100 m s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100 m s, the internal automatic programming cycle will commence. there is no page write window limitation. effectively the page write window is in?nitely wide, so long as the host continues to access the device within the byte load cycle time of 100 m s. hardware data protection the X28ST010 provides three hardware features that protect nonvolatile data from inadvertent writes. ? noise protectiona we pulse less than 10ns will not initiate a write cycle. ? default v cc senseall functions are inhibited when v cc is 3.4v. ? write inhibitholding either oe low, we high, or ce high will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. system considerations because the X28ST010 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple i/o pins share the same bus. it has been demonstrated that markedly higher temperature performance can be obtained from this device if ce is left enabled throughout the read and write operation. to gain the most bene?t it is recommended that ce be decoded from the address bus and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. because the X28ST010 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause transient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of the i/os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recommended that a 0.1 m f high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended that a 4.7 m f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces.
X28ST010 4 absolute maximum ratings* temperature under bias X28ST010 .......................................C55 c to +185 c voltage on any pin with respect to v ss ......................................... C1v to +7v d.c. output current .................................................... 5ma lead temperature (soldering, 10 seconds) ................................... 300 c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommend operating conditions temperature min. max. high temp. 0 c +185 c 5% supply voltages limits X28ST010 5v 5% back bias voltage: v C3v 5% d.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) notes: (1) v il min. and v ih max. are for reference only and are not tested. symbol parameter limits units test conditions min. max. i cc v cc current (active) (ttl inputs) 50 ma ce = oe = v il , we = v ih , all i/os = open, address inputs = .4v/2.4v levels @ f = 5mhz i sb1 v cc current (standby) (ttl inputs) 3ma ce = v ih , oe = v il all i/os = open, other inputs = v ih i li input leakage current 20 m a v in = v ss to v cc i lo output leakage current 20 m a v out = v ss to v cc , ce = v ih v ll (1) input low voltage C1 0.6 v v ih (1) input high voltage 2.2 v cc + 1 v v ol output low voltage 0.5 v i ol = 1ma v oh output high voltage 2.6 v i oh = C400 m a i bb back bias current 200 m a v bb = C3v 10%
X28ST010 5 power-up timing capacitance t a = +25 c, f = 1mhz, v cc = 5v endurance and data retention symbol parameter max. units t pur (2) power-up to read operation 100 m s t puw (2) power-up to write operation 5 ms symbol parameter max. units test conditions c i/o (2) input/output capacitance 10 pf v i/o = 0v c in (2) input capacitance 10 pf v in = 0v parameter min. max. units endurance 10,000 cycles per byte data retention 100 years a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v equivalent a.c. load circuit notes: (2) this parameter is periodically sampled and not 100% tested. symbol table 5v 1.92k w 100pf output 1.37k w waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance mode selection ce oe we mode i/o power l l h read d out active l h l write d in active h x x standby and high z standby write inhibit x l x write inhibit x x h write inhibit
X28ST010 6 a.c. characteristics (over the recommended operating conditions, unless otherwise specified.) read cycle limits read cycle notes: (3) t lz min.,t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf, from the point when ce or oe return high (whichever occurs ?rst) to the time when the outputs are no longer driven. symbol parameter X28ST010-20 X28ST010-25 units min. max. min. max. t rc read cycle time 200 250 ns t ce chip enable access time 200 250 ns t aa address access time 200 250 ns t oe output enable access time 50 50 ns t lz (3) ce low to active output 0 0 ns t olz (3) oe low to active output 0 0 ns t hz (3) ce high to high z output 50 50 ns t ohz (3) oe high to high z output 50 50 ns t oh output hold from address change 0 0 ns t ce t rc address ce oe we data valid data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z
X28ST010 7 write cycle limits we controlled write cycle notes: (4) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum tim e the device requires to complete internal write operation. symbol parameter min. max. units t wc (4) write cycle time 10 ms t as address setup time 20 ns t ah address hold time 100 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 200 ns t oes oe high setup time 10 ns t oeh oe high hold time 10 ns t wp we pulse width 200 ns t wph we high recovery 200 ns t dv data valid 1 m s t ds data setup 100 ns t dh data hold 25 ns t dw delay to next write 10 m s t blc byte load cycle 0.4 100 m s address t as t wc t ah t oes t dv t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp t wph
X28ST010 8 ce controlled write cycle page write cycle notes: (5) between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. (6) the timings shown above are unique to page write operations. individual byte load operations within the page write must conf orm to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t wph t cs t dv t ds t dh t ch ce we oe data in data out high z data valid t cw we oe last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce *address (6) i/o *for each successive write within the page write operation, a 8 Ca 16 should be the same or writes to an unknown address could occur.
X28ST010 9 packaging information 0.620 (15.75) 0.590 (14.99) typ. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) typ. 0.100 (2.54) 1.690 (42.95) max. 0.023 (0.58) 0.014 (0.36) typ. 0.018 (0.46) 0.232 (5.90) max. 0.060 (1.52) 0.015 (0.38) 3926 fhd f09 pin 1 0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.033 (0.84) typ. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) max. 0 15 32-lead hermetic dual in-line package type d note: all dimensions in inches (in parentheses in millimeters) 0.005 (0.13) min. 0.150 (3.81) min. 0.015 (0.38) 0.008 (0.20) seating plane
X28ST010 10 packaging information 32-lead ceramic flat pack type f 3926 fhd f20 note: all dimensions in inches (in parentheses in millimeters) 0.019 (0.48) 0.015 (0.38) 0.045 (1.14) max. pin 1 index 132 0.120 (3.05) 0.090 (2.29) 0.045 (1.14) 0.026 (0.66) 0.007 (0.18) 0.004 (0.10) 0.370 (9.40) 0.270 (6.86) 0.830 (21.08) max. 0.050 (1.27) bsc 0.488 0.430 (10.93) 0.347 (8.82) 0.330 (8.38) 0.005 (0.13) min. 0.030 (0.76) min 1.228 (31.19) 1.000 (25.40)
X28ST010 11 packaging information 3926 fhd f21 36-lead ceramic pin grid array package type k 15 17 19 21 22 14 16 18 20 23 10 9 27 28 8 7 29 30 5 2 36 34 32 4 3 1 35 33 typ. 0.100 (2.54) all leads pin 1 index note: leads 5, 14, 23, & 32 12 11 25 26 13 6 31 24 typ. 0.180 (.010) (4.57 .25) 4 corners 0.770 (19.56) 0.750 (19.05) sq a a 0.185 (4.70) 0.175 (4.45) 0.020 (0.51) 0.016 (0.41) 0.072 (1.83) 0.062 (1.57) 0.120 (3.05) 0.100 (2.54) note: all dimensions in inches (in parentheses in millimeters) typ. 0.180 (.010) (4.57 .25) 4 corners 0.050 (1.27) 0.008 (0.20) a a
X28ST010 12 packaging information 32-lead ceramic small outline gull wing package type r 3926 fhd f27 notes: 1. all dimensions in inches 2. formed lead shall be planar with respect to one another within 0.004 inches 0.340 0.007 see detail a for lead information 0.440 max. 0.560 nom. 0.0192 0.0138 0.050 0.750 0.005 0.840 max. 0.060 nom. 0.020 min. 0.015 r typ. 0.035 min. 0.015 r typ . 0.035 typ . . detail a 0.560" typical 0.050" typical 0.050" typical footprint 0.030" typical 32 places 0.165 typ
X28ST010 13 ordering information limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?cation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the f reedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?tness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874 , 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. device access time C20 = 200ns C25 = 250ns temperature range blank = commercial = 0 c to 185 c package d = 32-lead cerdip f = 32-lead flat pack k = 36-lead pin grid array r = 32-lead ceramic soic X28ST010 x -x x

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